1. Field of the Invention
The invention is related to the field of communications, and in particular, to crossbar integrated circuits that provide switching capability within communication devices.
2. Statement of the Problem
There is a great demand for communication devices that operate at higher and higher speeds. High-speed communications require that a synchronized clock be available throughout the communication device, so the various elements of the communication device can inter-operate properly. Unfortunately, the clock circuitry in high-speed communication devices requires excessive power and physical space.
FIG. 1 illustrates communication device 100 in the prior art. Some examples of communication device 100 include switch fabrics, switches, and routers. Communication device 100 includes communication processing circuitry 101 and crossbar integrated circuits 102–104. Communication processing circuitry 101 is coupled to incoming communication links 111 and outgoing communication links 118. Communication processing circuitry 101 is coupled to crossbar integrated circuit 102 by incoming serial channels 112 and outgoing serial channels 115. Communication processing circuitry 101 is coupled to crossbar integrated circuit 103 by incoming serial channels 113 and outgoing serial channels 116. Communication processing circuitry 101 is coupled to crossbar integrated circuit 104 by incoming serial channels 114 and outgoing serial channels 117.
Links 111 and 118 transfer communications to and from communication device 100. Links 111 and 118 could use electrical, optical, or wireless media to transfer the communications using various communication protocols. Some common protocols are Synchronous Optical Network (SONET), Asynchronous Transfer Mode (ATM), Internet Protocol (IP), Code Division Multiple Access (CDMA), and Ethernet.
Communication processing circuitry 101 exchanges the communications with links 111 and 118. Communication processing circuitry 101 also exchanges the communications with crossbar integrated circuits 102–104. Communication processing circuitry 101 handles physical layer tasks to interface with the particular type of media used by links 111 and 118. Communication processing circuitry 101 handles link layer tasks to process the particular protocols used on links 111 and 118. Communication processing circuitry 101 handles network layer tasks to properly route the communications from incoming links 111 to outgoing links 118. In response to control signals from communication processing circuitry 101, crossbar integrated circuits 102–104 switch the communications from incoming serial channels 112–114 to the proper outgoing serial channels 115–117. Crossbar integrated circuits 102–104 are silicon chips configured with controllable cross-point matrices that perform the switching.
In operation, communication processing circuitry 101 receives and processes communications from incoming links 111 to apply physical layer, link layer, and network layer functionality. Communication processing circuitry 101 transfers the communications to crossbar integrated circuits 102–104 over incoming channels 112–114. To implement routing, crossbar integrated circuits 102–104 switch the communications from incoming channels 112–114 to the proper outgoing channels 115–117. Communication processing circuitry 101 transfers the switched communications to outgoing links 118.
To provide a synchronized clock, communication processing circuitry 101 and crossbar integrated circuits 102–104 share clock information over serial channels 112–117. An individual serial channel transfers communications in a single stream of bits. Clock recovery entails analyzing the received bits to determine bit arrival times and recovering the clock based on these times. Clock encoding entails ensuring that enough transitions between logic states are present in the bits to allow for clock recovery. For serial channels 112–114, the clock information is encoded into the bits by communication processing circuitry 101 and is recovered from the bits by crossbar integrated circuits 102–104. For serial channels 115–117, the clock information is encoded into the bits by crossbar integrated circuits 102–104 and is recovered from the bits by communication processing circuitry 101. As mentioned above, the clock encoding and recovery circuitry requires excessive power and space.
FIG. 2 illustrates crossbar integrated circuit 202 in the prior art. Crossbar integrated circuit 202 includes serial channel interfaces 221–226 and crossbar matrix 240. Serial channel interfaces 221–223 are respectively coupled to incoming serial channels 231–233. Serial channel interfaces 221–223 are respectively coupled to crossbar matrix 240 by serial channels 241–243. Serial channel interfaces 224–226 are respectively coupled to outgoing serial channels 234–236. Serial channel interfaces 224–226 are respectively coupled to crossbar matrix 240 by serial channels 244–246. Crossbar matrix 240 includes cross-points that switch between incoming serial channels 241–243 and outgoing serial channels 244–246.
Serial channel interfaces 221–223 each include clock recovery circuits to recover clock information from the communications on incoming serial channels 231–233. Serial channel interfaces 224–226 each include clock encoding circuits to encode clock information into the communications on outgoing serial channels 234–236. The communication processing circuitry (not shown) on the opposite end of serial channels 231–233 includes clock encoding circuits to encode clock information into the communications on serial channels 231–233. The communication processing circuitry (not shown) on the opposite end of serial channels 234–236 includes clock recovery circuits to recover clock information from the communications on serial channels 234–236.